DMA問題
目前小妹用lm4f232h5qd的开发版，做多个串口的实验，小妹大致上是这样做的
UART1~UART5 个别利用5个UART中断接收资料
而UART0则是利用DMA将收到的资料送出
如果小妹向UART1与UART2同时送资料时，电脑终端机收到的资料是对的
但是向UART1~UART3同时送资料时，电脑终端机收到的资料确是错的
小妹找问题找了好久但始终找不到原因，可以帮帮忙吗?谢谢
感激不尽 ><
以下是小妹配置的程序
UART0 DMA 配置
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
//ROM_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UART0);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
// Configure the UART communication parameters.
ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE);
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
// Enable the UART for operation, and enable the uDMA interface for RX
// channels.
ROM_UARTEnable(UART0_BASE);
//ROM_UARTDMAEnable(UART0_BASE, UART_DMA_TX);
// Put the attributes in a known state for the uDMA UART0TX channel. These
// should already be disabled by default.
ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_UART0TX,
UDMA_ATTR_ALTSELECT |
UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK);
// Set the USEBURST attribute for the uDMA UART TX channel. This will
// force the controller to always use a burst when transferring data from
// the TX buffer to the UART. This is somewhat more effecient bus usage
// than the default which allows single or burst transfers.
ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_UART0TX, UDMA_ATTR_USEBURST);
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
ROM_uDMAChannelControlSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
UDMA_ARB_8);
其中一個UART中斷程式
void
UART1IntHandler(void)
{
unsigned long ulStatus;
char header[]="###B";
char tail[]="B%%%";
//get interrupt status
ulStatus = ROM_UARTIntStatus(UART1_BASE, true);
//clear the asserted interrupts
ROM_UARTIntClear(UART1_BASE, ulStatus);
//FIFO data transfer
//UARTprintf("\nInside the int\n");
//k++;
//if (k>8)k=0;
if(ulStatus == UART_INT_RX)//?交銝剜䦅璅?
{
//UARTprintf("\nk=%d\n",k);
while(ROM_UARTCharsAvail(UART1_BASE)) //loop while there are chars
{
g_ucRxBuf1 = ROM_UARTCharGetNonBlocking(UART1_BASE);
if(g_ulRxBuf1Count >= UART_RXBUF_SIZE)
{
counter++;
g_ulRxBuf1Count = 0;
memcpy(uartTmpBuff,header,sizeof(header));
memcpy(uartTmpBuff+sizeof(header)-1,g_ucRxBuf1,sizeof(g_ucRxBuf1));
memcpy(uartTmpBuff+sizeof(header)+sizeof(g_ucRxBuf1)-1,tail,sizeof(tail));
//???唾撓閮剔蔭
ROM_uDMAChannelTransferSet(UDMA_CHANNEL_UART0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, uartTmpBuff,
(void *)(UART0_BASE + UART_O_DR),
sizeof(uartTmpBuff));
ROM_uDMAChannelEnable(UDMA_CHANNEL_UART0TX);
}
}
}
}
硬件连接是否正确？
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